The subject invention relates to a MOS semiconductor device with high concentration and high reliability, wherein miniaturization has been achieved, driving capabilities have been improved and furthermore resistance to hot carriers has been improved; and its fabricating method.
In ultra integrated circuit devices, so-called VSLI and MOS semiconductor devices are being miniaturized to the sub-micron region due to the demands of high integration. Accompanying this miniaturization, the degradation of electrical characteristics due to hot carriers has become a serious problem from the standpoint of reliability. As a MOS structure to improve resistance to hot carriers and moreover to improve driving capabilities, the sidewall gate structure has been proposed. For example, as proposed by I-C Chen, et al. in I.E.E.E. Electron Device Letters, Vol. 11, No. 2, February 1990, pp 78-81.
On the one hand, structures and processes have been proposed to miniaturize the source-drain electrode regions when miniaturization is advanced into the submicron region and smaller regions. For example, a SSSMOS structure has been proposed by C. K. Lau, et al. in I.E.E.E. 1987 I.E.D.M. Technical Digest, pp 358-361.
We shall now explain this from two objectives accompanying the miniaturization of MOS semiconductor devices:
(I) Improvement of resistance to hot carrier degradation and improvement of driving capabilities, and, PA1 (II) Miniaturization of the source-drain electrode region. PA1 (I) With regard to improvement of resistance to hot carrier degradation and improvement of driving capabilities: PA1 (II) With regard to miniaturization of the source-drain electrode: PA1 (1) Because the sidewall gate electrode 37 is formed above the low concentration diffusion layer 33, the effective channel length, L.sub.eff becomes: EQU L.sub.eff &gt;L.sub.g -2.times.L.sub.s PA1 (2) Because the sidewall gate electrode 37 is formed above the low concentration diffusion layer 33, in order to obtain contacts for the source-drain electrode, a rather broad margin of contact is required, taking into account insulation vis-a-vis the sidewall gate electrode 37. Hence, miniaturizaton is difficult. PA1 (1) With respect to the hot carrier degradation, which becomes a severe problem in micro-MOS semiconductors in the submicron region and smaller, since 150 nm insulating film sidewall 47 is formed, unlike the prior art LDD structure, the high electrical field generated within the low concentration diffusion layer 43 is not sufficiently ameliorated at the gate electrode 45, and the generation of hot carriers is not sufficiently suppressed. Also, traps and boundary levels are generated in the sidewall 47 above the low concentration diffusion layer 43, and there is severe early degradation of electrical characteristics due to hot carrier degradation. PA1 (2) Because the insulating film sidewall 47 is formed above the low concentration diffusion layer 43, the potential of the low concentration diffusion layer 43 is not sufficiently controlled at the gate electrode 45, the accumulation of the low concentration diffusion layer 43 is not promoted, the source resistance is high and the driving capabilities are lowered. PA1 (3) Since the source-drain regions are formed in a self aligning manner, the processes of forming and removing a nitride film sidewall are required, and additionally, in order to form the high concentration diffusion film 42, there is the added process of selectively growing a monocrystalline silicon film epitaxially and, the fabrication process itself becomes complex.
As an example, the sidewall gate structure proposed by I-C Chen, et al. in I.E.E.E. Electron Device Letters, Vol. 11, No. 2, February 1990, pp 78-81, is shown in FIG. 6.
In FIG. 6, 31 is a semiconductor substrate of a first conductivity type (P type), 32 is a high concentration source-drain diffusion layer of a second conductivity type (n+type) formed on the surface of the semiconductor substrate 31, 33 is a low concentration diffusion layer of a second conductivity type (n-type) likewise formed on the surface of the semiconductor substrate 31. 34 is the gate oxide film, 35 is the gate electrode, 36 is an oxide layer formed to cover the gate electrode, and, 37 is the sidewall gate electrode.
In this type of MOS semiconductor device structure, since the sidewall gate electrode 37 is formed above the low concentration diffusion layer 33 through the medium of the gate oxide film 34, the high electrical field generated within the low concentration diffusion layer 33 is mitigated, the generation of hot carriers is suppressed and resistance to degradation is improved. Also, by controlling the potential of the high resistance low concentration diffusion layer 33 by the sidewall gate electrode 37, the accumulation of the low concentration diffusion layer 33 is promoted, the source resistance is lowered and driving capabilities are improved.
As an example, FIG. 7 shows the structure proposed by C. K. Lau et al. in I.E.E.E. 1987 I.E.D.M. Technical Digest, pp 358-361.
In FIG. 7, 41 is a semiconductor substrate of a first conductivity type (p type), 42 is a high concentration diffusion layer of a second conductivity type (n+type), 43 is a low concentration diffusion layer of a second conductivity type (n-type), 44 is a gate oxide film, 45 is a gate electrode, 46 is an insulator film, 47 is a sidewall, 48 is a tungsten electrode and 49 is a field oxide film.
In this type of MOS semiconductor device structure, after forming a standard type gate electrode 45 by the 1 micron process, a 250 to 300 nm sidewall of nitride film (not shown) is formed, and the source-drain region is formed through an oxidation process at 950.degree. C. After removing the sidewall of nitride film, the low concentration diffusion layer 43 is formed by ion implantation. After forming a 150 nm sidewall 47, ion implantation is used to form the high concentration diffusion layer 42.
However, this structure and fabrication process still does not suffice for a MOS semiconductor device for the submicron region and smaller regions. That is to say, the MOS semiconductor device shown in FIG. 6 has the following serious problems:
Here, L.sub.g is the total gate length and L.sub.s is the length of the sidewall gate. Since the sidewall gate length L.sub.s needs to be at least 0.15 microns, it is not possible to make structures each with a gate length L.sub.g of 0.3 microns or less.
From the above points, it is extremely difficult to miniaturize the sidewall gate structure to the submicron region and less.
Also, in the MOS semiconductor device with the structure shown in FIG. 7, the following severe problems exist: